PRELIMINARY DATA SHEET
VDP 31xxB
FP Sub-
address
Function
Default
Name
DVCO
h’f8
h’f9
crystal oscillator center frequency adjust, –2048 ... 2047
–720 dvco
crystal oscillator center frequency adjustment value for line lock mode,
true adjust value is DVCO – ADJUST.
read only adjust
For factory crystal alignment, using standard video signal:
set DVCO = 0, set lock mode, read crystal offset from ADJUST register
and use negative value for initial center frequency adjustment via DVCO.
h’f7
crystal oscillator line-locked mode, lock command/status
0
xlck
write: 100
0
read: 0
enable lock
disable lock
unlocked
locked
>2047
FP Status Register
h’12
general purpose control bits
bit[2:0]
bit[3]
bit[8:4]
bit[9]
reserved, do not change
vertical standard force
reserved, do not change
disable flywheel interlace
reserved, do not change
0
1
vfrc
dflw
bit[11:10]
to enable vertical free run mode set vfrc to 1 and dflw to 0
standard recognition status
h’13
–
asr
bit[0]
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
bit[7]
bit[8]
bit[9]
bit[11:10]
1
1
1
1
1
1
1
1
1
1
vertical lock
horizontally locked
no signal detected
color amplitude killer active
disable amplitude killer
color ident killer active
disable ident killer
interlace detected
no vertical sync detection
spurious vertical sync detection
reserved
h’cb
h’15
h’74
h’31
h’f0
number of lines per field, P/S: 312, N: 262
vertical field counter, incremented per field
measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC)
measured burst amplitude
read only nlpf
vcnt
read only sampl
read only bampl
read only sw_version
firmware version number
bit[7:0]
bit[11:8]
internal revision number
firmware release
h’f1
hardware version number
read only hw_version
bit[7:0]
internal hardware revision number
bit[11:8]
hardware id
0000 = VDP 3120B
1000 = VDP 3116B
0100 = VDP 3112B
1100 = VDP 3108B
1110 = VDP 3104B
Micronas
41
MICRONAS [ MICRONAS ]
