PRELIMINARY DATA SHEET
VDP 31xxB
2
I C sub
Number
Mode
Function
Default
Name
address of bits
TIMING
h’67
h’77
h’73
9
w v
w v
w v
vertical blanking start
bit [8:0]
0..511
first line of vertical blanking
305
25
30
0
VBST
VBSO
AVST
STIMP
9
9
vertical blanking stop
bit [8:0] 0..511
last line of vertical blanking
start of Black Level Expander measurement
bit [8:0]
line
0..511
first line of measurement, stop with first
of vertical blanking
h’5f
9
w v
bit [8:0] free running field period = (value)4) lines
HORIZONTAL DEFLECTION
h’7a
9
9
9
w v
w v
w v
adjustable delay of PLL2, clamping, and blanking (relative to
front sync)
adjust clamping pulse for analog RGB input
–141
0
POFS2
POFS3
HPOS
bit [8:0]
–256..+255 " 8 µs
h’76
h’7e
adjustable delay of flyback, main sync, csync and analog RGB
(relative to PLL2)
adjust horizontal drive or csync
bit [8:0]
–256..+255 "8 µs
adjustable delay of main sync (relative to flyback)
adjust horizontal position for digital picture
120
bit [8:0]
20 steps+1 µs
h’5b
h’57
9
9
w/r
w/r
start of horizontal blanking
bit [8:0] 0..511
1
HBST
HBSO
end of horizontal blanking
bit [8:0] 0..511
48
PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number)
–n–1
h’6a
h’6e
h’72
9
9
9
w v
w v
w v
bit [5:0]
bit [5:0]
bit [5:0]
proportional coefficient PLL3, 2
proportional coefficient PLL2, 2
integral coefficient PLL2, 2
2
1
2
PKP3
PKP2
PKI2
–n–1
–n–5
h’15
16
w/r
horizontal drive and vertical signal control register
32
HDRV
bit [5:0]
0..63
horizontal drive pulse duration in ms
(internally limited to 4..61)
EHPLL
EFLB
bit [6]
bit [7]
0/1
0/1
disable/enable horizontal PLL2 and PLL3
1: disable horizontal drive pulse during
flyback
0
0
bit [8]
bit [9]
bit [10]
0/1
0/1
0/1
reserved, set to ’0’
enable/disable ultra black blanking
0: all outputs blanked
DUBL
EBL
0
1
1: normal mode
DCRGB
SELFT
bit [11]
bit [12]
0/1
0/1
enable/disable clamping for analog RGB
input
0
0
disable/enable vertical free running mode
(FIELD is set to field2, no interlace)
enable/disable vertical protection
internal/external (under VPC control)
start of vertical and E/W signal
disable/enable phase shift of display clock
DVPR
XDEFL
bit [13]
bit [14]
0/1
0/1
0
0
DISKA
bit [15]
0/1
1
Micronas
37
MICRONAS [ MICRONAS ]
