PRELIMINARY DATA SHEET
VDP 31xxB
Table 3–3: Control Registers of the Fast Processor for control of front-end functions
– default values are initialized at reset
FP Sub-
address
Function
Default
Name
Standard Selection
h’20
Standard select:
0
sdt
bit[2:0]
standard
0
1
2
3
4
5
6
7
PAL B,G,H,I (50 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
pal
ntsc
NTSC M
SECAM
NTSC44
PAL M
PAL N
PAL 60
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
secam
ntsc44
palm
paln
pal60
ntscc
sdtmod
NTSC COMB(60 Hz)
bit[3]
0/1 standard modifier
PAL modified to simple PAL
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
bit[4]
bit[5]
bit[6]
reserved (set to 0)
0/1 2-H comb filter off/on
0/1 S-VHS mode off/on
comb
svhs
Option bits allow to suppress parts of the initialization, this can be used
for color standard search:
sdtopt
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
2-H comb filter set-up only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
h’22
h’23
picture start position, this register sets the start point of active video, this
can be used e.g. for panning. The setting is updated when ’sdt’ register
is updated.
0
0
sfif
luma/chroma delay adjust. The setting is updated when ’sdt’ register is
ldly
updated.
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ... –7
Micronas
39
MICRONAS [ MICRONAS ]
