VDP 31xxB
PRELIMINARY DATA SHEET
FP Sub-
address
Function
Default
Name
Scaler Control Register
h’40
scaler mode register
0
scmode
pano
bit[1:0]
scaler mode
0
1
2
3
linear scaling mode
nonlinear scaling mode, ’panorama’
nonlinear scaling mode, ’waterglass’
reserved
bit[10:2]
bit[11]
reserved, set to 0
scaler update
0
start scaler update command,
when the registers are updated the bit is set to 1
h’41
luma offset register
bit[6:0] luma offset 0..127
ITU-R output format:
CVBS output format:
57 yoffs
57
4
this register is updated when the scaler mode register is written
h’42
h’43
active video length for 1-h FIFO
1080 fflim
bit[11:0]
length in pixels
this register is updated when the scaler mode register is written
scaler1 coefficient, this scaler is compressing the signal.
For compression by a factor c the value c*1024 is required.
scinc1
bit[11:0]
allowed values from 1024..4095
1024
this register is updated when the scaler mode register is written
h’44
h’45
scaler2 coefficient, this scaler is expanding the signal.
For expansion by a factor c the value 1/c*1024 is required.
scinc2
bit[11:0]
allowed values from 256..1024
1024
this register is updated when the scaler mode register is written
scaler1/2 nonlinear scaling coefficient
this register is updated when the scaler mode register is written
0
0
scinc
h’47 –
h’4b
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
scw1_0 – 4
h’4c –
h’50
scaler2 window controls see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
0
scw2_0 – 4
42
Micronas
MICRONAS [ MICRONAS ]
