SDA9410
Preliminary Data Sheet
Application modes and memory concept
Steps MEM- ORG-
ORG-
MEMS
MEM- MEM- MEM- Operation
OP
MEMM
WRM
WRS
RDS
6
7
01
0
1
1
0
X
changing picture sizes of master and slave by
programming the corresponding decimation
I²C Bus parameters
01
1
1
0
0
X
reducing the width below 512 pixel for the
master picture two fields can be stored
Table 57
Changing the picture sizes to double window format
Starting in SRC mode with a PIP insertion (step 1) at first a field based up conversion
mode must be chosen for both channels, e.g. AABB conversion for interlaced modes and
intrafield interpolation for progressive modes (step 2). Now the capacity for the master
channel can be reduced to 1 field (step 3). The free memory capacity is used to write the
slave data at two address areas in parallel corresponding to SRC-PIP configuration and
SSC configuration. In step 4 the reading of the slave channel data is switched to SSC
configuration. In the last step also the master channel is switched to SSC mode. In this
configuration we can store 1 field of the master channel and 2 fields of the slave channel.
The Joint Line Controller can be activated and joint line free display is possible.
Reducing the size of the master picture and enlarging the slave picture size is performed
in step 6 in table . During this phase we can get problems with joint line free display of
the master picture until the horizontal width is below 512 pixel. Now also the master
channel is enabled to store 2 fields and joint line free display is possible again (step 7).
In this configuration double window display is performed.
During all steps positioning of both pictures is free programmable to enable multiple
variations of the animation.
M
S
M
S
SSC-Mode, AABB (A+B):
SRC-PIP Mode, ABAB (A+B)
-master picure becomes smaller
-slave picture becomes larger
Figure 28
Completing the operations to a master slave exchange
65
Micronas
MICRONAS [ MICRONAS ]
