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SDA9410-B13 参数 Datasheet PDF下载

SDA9410-B13图片预览
型号: SDA9410-B13
PDF下载: 下载PDF文件 查看货源
内容描述: 显示处理器,并采用扫描率转换器的嵌入式DRAM技术单位 [Display Processor and Scan Rate Converter using Embedded DRAM Technology Units]
分类和应用: 转换器动态存储器
文件页数/大小: 179 页 / 3137 K
品牌: MICRONAS [ MICRONAS ]
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SDA9410  
Preliminary Data Sheet  
Application modes and memory concept  
4:2:2  
4:1:1  
4:2:0  
Y0  
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1. line  
2. line  
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3. line  
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Figure 25  
Supported data formats  
Additionally 3 fields of a decimated picture of the slave channel with the size of up to 1/  
9 of the original format can be stored (4:1:1 or 4:2:0 format). In this mode motion  
estimation and compensation (Micronas VDU algorithm) for the master channel is  
supported (up to 30 MHz clock frequency). In parallel it is possible to insert the slave  
channel at any display position using frame mode and without joint lines. Noise reduction  
algorithm by recursive filtering is supported only for the master channel in SRC-Mode.  
In SSC-Mode the data configuration of master and slave channel can be different.  
Depending on the picture size it is possible to store only 1 field of luminance and  
chrominance data or 2 fields. The data configuration can be defined by the I²C Bus  
parameters ORGMEMM and ORGMEMS, respectively.  
ORGMEMM  
Data configuration of the memory  
2 fields (limited picture size in SSC- and MUP-Mode)  
1 field  
1
0
Table 39  
Definition of ORGMEM  
ORGMEMS  
Data configuration of the memory  
1
3 fields PIP (SRC-Mode),  
2 fields (restricted picture size, SSC and MUP Mode)  
0
Slave channel blocked (SRC-Mode and ORGMEMM=1)  
1 field (SSC- and MUP-Mode; SRC-Mode and ORGMEMM=0)  
Table 40  
Definition of ORGMEMS  
55  
Micronas  
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