SDA9410
Preliminary Data Sheet
Application modes and memory concept
I²C Bus
Sub address
Description
parameter
PLLMOFF
1: off
00h
PLLM master channel on or off, only for test purpose
0: on
PLLMRA
00h
22h
PLLM range, only for test purpose
PLLSOFF
1: off
PLLS slave channel on or off, only for test purpose
0: on
PLLSRA
22h
5Fh
PLLS range
PLLDOFF
1: off
PLLD display channel on or off, only for test purpose
0: on
PLLDRA
5Fh
5Fh
PLLD range
CLKOUTON
1: enabled
0: disabled
Output of system clock CLKOUT
CLKMDEN
1: X1/CLKD
0: CLKM
5Fh
Input clock for PLLD
Table 36
5.6
Input write I²C Bus parameter
Application modes and memory concept
Introduction
5.6.1
The Main Memory of the SDA 9410 has an overall capacity of 6 Mbit. It is divided into
two identical and independent 3 Mbit parts.
The Main Memory has 2 completely independent data inputs (master and slave channel)
to enable a multitude of PIP features. In general the channels are asynchronous having
2 separate clock PLLs (CLKM, CLKS). Reading of master and slave data for display is
performed using a third asynchronous clock (CLKD). In this way a decoupling of input
and output clocks is achieved.
The Main Memory supports different operation modes of the SDA 9410 by adapted data
configurations. The different modes are defined by the I²C Bus parameter MEMOP (I²C
Bus sub address 53h).
53
Micronas
MICRONAS [ MICRONAS ]
