SDA9410
5.5
Preliminary Data Sheet
Clock concept
Clock concept
Signals
CLKM
Pin number
Description
18
58
2
System clock input master channel
System clock input slave channel
System clock input display channel
CLKS
X1/CLKD
Table 33
Input signals
Signals
Pin number
Description
CLKOUT
3
Clock output
Table 34
Output signals
The SDA 9410 supports different clock concepts. The Figure 24 shows a typical
application of the SDA 9410. The frontend clock is connected to CLKM input. The
second frontend clock is connected to CLKS input. The CLKOUT pin is connected to the
backend and the X1/CLKD input is connected to a crystal oscillator. The Figure 23
explains the clock switch, which may be used for the separate modes (see also Table
37 "Ingenious configurations of the HOUT and VOUT generator" on page 80).
PLLS
PLLM
CLKS
CLKM
CLKS_pll
CLKM_pll
CLKD_pll
0
1
PLLD
CLKOUT
X1/CLKD
CLKMDEN
Figure 23
Clock concept of SDA 9410
51
Micronas
MICRONAS [ MICRONAS ]
