SDA9410
Preliminary Data Sheet
Clock concept
YUVINM
Y
U
V
Y
U
V
R
G
B
8
HINM
SDA
9206
Analog
CVBS
colour
VINM
decoder
ABACUS
SYNC
CLKM = 27 MHz
SDA 9380
Deflection
controller
+
SDA
9410
YUVINS
Y
U
V
H-Drive
V-Drive
RGB
VOUT
8
DAEDALUS
processing
HINS
HOUT
SDA
9206
Analog
colour
CVBS
VINS
CLKOUT
decoder
ABACUS
CLKS = 27 MHz
E/W
SYNC
Figure 24
Application for SDA 9410
CLKMDEN (5Fh)
PLLD input
CLKM
0
1
X1/CLKD
Clock
Used in block
CLKM_pll
CLKS_pll
CLKD_pll
ISCM, IFCM, VHCOMM, TSNR, LBD, LM, I²C
ISCS, IFCS, VHCOMS, LM, I²C
OSCM/S, ME, SRCM, SRCS, ED, MC, LM, DLTI, DCTI, Peaking, DAC, I²C
Table 35
Clock concept switching matrix
52
Micronas