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SDA9410-B13 参数 Datasheet PDF下载

SDA9410-B13图片预览
型号: SDA9410-B13
PDF下载: 下载PDF文件 查看货源
内容描述: 显示处理器,并采用扫描率转换器的嵌入式DRAM技术单位 [Display Processor and Scan Rate Converter using Embedded DRAM Technology Units]
分类和应用: 转换器动态存储器
文件页数/大小: 179 页 / 3137 K
品牌: MICRONAS [ MICRONAS ]
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SDA9410  
Preliminary Data Sheet  
Input format conversion (IFCM/IFCS)  
In case of CCIR 656 three modes are supported (FORMATM/FORMATS=11 means full  
CCIR 656 support, including H-, V-Sync and Field signal, FORMATM/FORMATS=01  
means only data processing, H- and V-Sync have to be added separately according  
PAL/NTSC norm, FORMATM/FORMATS=10 means only data processing, H- and V-  
sync have to be added separately according CCIR656-PAL/NTSC norm). The  
representation of the samples of the chrominance signal is programmable as positive  
dual code (unsigned, I²C Bus parameter TWOINM/TWOINS=0) or two's complement  
code (TWOINM/TWOINS=1, "I²C Bus" on page 117, I²C Bus parameter 0Bh,2Dh).  
Inside the SDA 9410 all algorithms assume positive dual code.  
FORMATM/  
FORMATS  
HINS/HINS  
VINM/VINS  
YINM/YINS  
UVINM/UVINS  
00  
PAL/NTSC  
PAL/NTSC  
PAL/NTSC  
PAL/NTSC  
4:2:2  
4:2:2  
x
01 (CCIR 656 only  
data)  
CCIR 656  
10  
CCIR 656  
x
CCIR 656  
x
CCIR 656  
CCIR 656  
x
x
11 (full CCIR 656)  
Table 9  
Input sync formats  
The amplitude resolution for each input signal component is 8 bit, the maximum clock  
frequency is 27 MHz. Consequently the SDA 9410 is dedicated for application in high  
quality digital video systems.  
27  
Micronas  
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