SDA9410
Preliminary Data Sheet
Input sync controller (ISCM/ISCS)
I²C Bus parameter
[Default value]
Sub address
12h
Description
NALIPM
[20]
Not Active Line InPut Master defines the number of lines from
the V-Sync to the first active line of the field
NALIPS
[20]
34h
Not Active Line InPut Slave defines the number of lines from
the V-Sync to the first active line of the field
ALPFIPM
[144]
10h
Active Lines Per Field InPut Master defines the number of
active lines
ALPFIPS
[144]
32h
Active Lines Per Field InPut Slave defines the number of active
lines
NAPLIPM
NAPIPDLM
[0]
NAPIPPHM
[0]
03h, 0Ch
Not Active Pixels Per Line InPut Master defines the number of
pixels from the H-Sync to the first active pixel of the line. The
number of pixels is a combination of NAPIPDLM and
NAPIPPHM.
NAPLIPS
NAPIPDLS
[0]
2Dh, 2Eh
Not Active Pixels Per Line InPut defines the number of pixels
from the H-Sync to the first active pixel of the line. The number
of pixels is a combination of NAPIPDLS and NAPIPPHS.
NAPIPPHS
[0]
APPLIPM
[180]
0Fh
31h
Active Pixels Per Line InPut Master defines the number of
active pixels
APPLIPS
[180]
Active Pixels Per Line InPut Slave defines the number of active
pixels
Table 3
Input write I²C Bus parameter
Inside of the SDA 9410 a field detection block is necessary for the detection of an odd
(A) or even (B) field. Therefore the incoming H-Sync H1 (delayed HINM/HINS signal,
delay depends on NAPIPDLM/NAPIPDLS and NAPIPPHM/NAPIPPHS) is doubled (H2
signal). Depending on the phase position of the rising edge of the VINM/VINS signal an
A (rising edge between H1 and H2) or B (rising edge between H2 and H1) field is
detected. For proper operation of the field detection block, the VINM/VINS must be
delayed depending on the delay of the HINM/HINS signal (H1). The figure below
explains the field detection process and the functionality of the VINDELM/VINDELS I²C
Bus parameter (inside the SDA 9410 the delayed VINM/VINS signal is called Vd and the
detected field signal is called Ffd).
23
Micronas
MICRONAS [ MICRONAS ]
