SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS)
The Figure 9 shows the generation of the internal H- and V-syncs in case of full CCIR
656 mode. The H656 sync is generated after the EAV. The V656 and F656 signals
change synchronously with the EAV timing reference code.
CLK1 (27 MHz)
CCIR 656 interface
EAV
SAV
u0
y0
v0
y1
u2
y3
EAV
YIN
288 Tclk1(PAL)
276 Tclk1(NTSC)
1728 Tclk1(PAL)
1716 Tclk1(NTSC)
CLK1 (27 MHz)
YIN
x
EAV
x
x
SAV
x
x
EAV
x
H656
V656
(e.g.)
F656
(e.g.)
F = 0 during field 1(A)
F = 1 during field 2(B)
EAV
SAV
11111111
00000000
00000000
00000000
1FV1P3P2P1P0
1FV0P3P2P1P0
MSB
LSB
V = 0 elsewhere
V = 1 during field blanking
11111111
00000000
Figure 9
Explanation of 656 format
The Figure 10 explains the functionality of the SYNCENM/SYNCENS signal. The SDA
9410 needs the SYNCENM/SYNCENS (synchronization enable) signal, which is used to
gate the YINM/YINS, UVINM/UVINS as well as the HINM/HINS and the VINM/VINS
signal. This is implemented for frontends which are working with 13.5 MHz and a large
output delay time for YINM/YINS, UVINM/UVINS, HINM/HINS and VINM/VINS (e.g.
Micronas VPC32XX, output delay: 35 ns). For this application the half system clock
CLKM/CLKS (13.5 MHz) from the frontend should be provided at this pin. In case the
frontend is working at 27.0 MHz with sync signals having delay times smaller than 25 ns,
this input can be set to low level (SYNCENM/SYNCENS=VSS) (e.g. Micronas SDA 9206,
output delay: 25 ns). Thus the signals YINM/YINS, UVINM/UVINS, HINM/HINS and
VINM/VINS are sampled with the CLKM/CLKS system clock when the SYNCENM/
SYNCENS input is low.
The Figure 10 shows the gated inputs signals YINMen, UVINMen, HINMen and
VINMen.
28
Micronas
MICRONAS [ MICRONAS ]
