SDA 9380 - B21
Preliminary Data Sheet
System description
The PLL control byte 0 includes the following bits:
0
0
X
INCR4
INCR3
INCR2
INCR1
INCR0
-INCR4..0: Nominal PLL output frequency
INCR=INT((FH*55296)/FQ-64.625)
(for typical values see table below)
specified range:6≤INCR≤21
(FQ=24.576MHz)
Application
PAL (50Hz)
NTSC (60Hz)
PAL (60Hz)
PAL (100Hz)
NTSC (120Hz)
ATV
FH[Hz]
15625
15750
18750
31250
31500
32400
33750
INCR
FH1_2
Low
6
6
Low
20
6
Low
High
High
High
High
6
8
11
MUSE
Macintosh
(640*480*67Hz)
35000
38000
14
21
High
High
SVGA
(800*600*60Hz)
Internal default value:
INCR = 6
if FH1_2 = High
INCR = 6
INCR = 20
if FH1_2 = Low, SSD = Low
if FH1_2 = Low, SSD = High
Default value read by IIC bus: INCR = 0
The PLL control byte 1 includes the following bits:
NOISY
VCR
0
0
0
GENMOD
VCR
HSWMI
TC_3RD
-GENMOD: Clock generator mode
0: normal PLL mode
1: generator mode (fixed frequency output, controlled by INCR..)
-VCR:
PLL filter optimized for
0: TV mode
1: VCR mode
Micronas
5-21
2001-01-29
MICRONAS [ MICRONAS ]
