CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
4.6.10. Registers
0200H
System Clock Prescaler
Bit
Reset
Read
Write
7 to 3
0
1
0
0
x
x
x
x
2
1
0
Divisor value –1
0201H
Bit
Control Register
Reset
Read
Write
7
copy
x
no function – set to ‘1’ (to keep
compatibility)
from
addr.
FFF9H
6
5
4
x
x
no function – set to ‘1’ (to keep
compatibility)
no function – set to ‘1’ (to keep
compatibility)
external bus: ‘1’ = bus on ports 0, 1, 2
disabled
Bus disable: ‘1” = disable bus on ports
0, 1, 2
3
2
R/W signal / Port4: ‘0’ = R/W, ‘1’ = P40
R/W signal / Port4: ‘0’ = R/W, ‘1’ = P40
ROM enable: ‘1’ = enable internal ROM
internal ROM: ‘1’ = internal ROM
enabled
1
0
internal RAM: ‘1’ = internal RAM enabled
internal CPU: ‘1’ = internal CPU enabled
RAM enable: ‘1’ = enable internal RAM
CPU enable: ‘1’ = enable internal CPU
0202H
Watchdog Control and Status
Bit
7
Reset
Read
Write
x
x
x
x
x
x
x
x
Watchdog time value =
f
system
6
x
(
Twd )
*
–1 = n
65536
5
x
T
= (n+1) * 65536
wd
f
system
4
x
(don’t use setting n<2!!)
with f = 4 MHz:
n = n
n = n
3
x
system
= 2
T
wdmin
= 49.152 ms
min
2
x
= 255
T
= 4.17792 s
max
wdmax
1
x
min. ∆n = 1
min. ∆T
=16.384 ms
wd
0
1/0
‘0’: last RESET was generated by
watchdog
38
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
