CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
4.6.5. Using external devices
nal devices for reading so that another few ns later they
drive the bus. The DATA BUS is used as DATA
MEMORY for a few ns. This is the only way to make sure
that, independent from the loads on the CCU address,
data and control lines collisions are avoided and a maxi-
mum of access time is available for the memory.
To avoid collision on the data bus during direction
changes, the CCU data bus out buffers (active during
PHI2=‘1’only)aredisabledbeforetheaddress, theR/W
and the R/W line changes (t
t t
This guarantees
DHW
AH).
that no collision happens on the bus if the output drives
of the external devices (ROM, RAM, Ports) are con-
trolled with the R/W or R/W signal and a read cycle fol-
lows a write cycle.
IF YOU WANT TO WRITE TO EXTERNAL DEVICES
THE DATA BUS MUST BE IN THE TRISTATE MODE
DURING WRITE OPERATIONS OF THE CCU. No pull-
up or pull-down resistors are allowed.
Important: In a write cycle the data-out drivers of the
CCU set up the data bus lines. Then they leave these
lines so that no drivers are active on the data bus. A few
ns later the R/WortheP5selectsignallatchthedatainto
the external device (Port out or Write into RAM). The
same signal is used to enable the output drivers of exter-
Eveninagoodlayoutthecapacitiveloadonthedatabus
is approx. 20 pF (2* pin capacity and layout). Even in the
worst case of a 1 MΩ leakage the time constant is
approx. 20 µs. The max. time between disabling the bus
drivers and the rising edge of R/W is 20 ns.
4.6.6. AC Characteristics at T = 0 °C to 65°C, V
= 5 V, f = 8 MHz, Cl = 0 pF
CLK
A
SUP
External Loads: add 0.75 ns/pF for controller output lines
Symbol
Parameter
Pin
Min.
125
60
10
15
20
10
9
Max.
2000
1000
22
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
Cycle Time (Processor)
Pulse Width Low
3
cyc
3
PWL
AH
Address Hold Time
Address Setup Time Read
Data Setup Time Read
Write Data Delay
26–41
34
ADS
DSR
MDS
DHW
DHR
RWH
WRH
18–25
–
29
Write Data Hold Time
Read Data Hold Time
Read/Write Hold Time
16
10
10
13
–
17
17
24
Read/Write Hold Time (P76 special
mode)
34
t
t
t
Delay P1 to P3 Select Lines on P5
Delay X1 to internalΦ2
42–47
12
7
26
15
10
ns
ns
ns
P5S
4
3
Φ
X1 2
Delay Φ2 internal to X2
5
Φ
2X2
34
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
