CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
4.6.7. IM Bus Waveforms
H
Ident
L
H
16
or
Clock
24
1
2
3
4
5
6
7
8
9
10 11 12 13
L
H
Data
LSB
Address
MSBLSB
Data
MSB
L
A
B
C
Section A
Section B
Section C
t
IM10
H
L
Ident
t
t
IM1
IM6
t
t
t
IM5
IM3
IM4
t
IM2
H
L
Clock
Data
t
t
t
IM8
IM9
IM7
H
L
Address LSB
Address MSB
Data MSB
Fig. 4–14: IM bus waveforms
4.6.8. Description of the IM Bus
as to switch the first bit on the Data line. Then eight ad-
dress bits are transmitted, beginning with the the LSB.
Data takeover in the slave ICs occurs at the positive
edge of the clock signal. At the end of the address byte
the ID signal switches to High, initiating the address
comparison in the slave circuits. In the addressed slave
the IM bus interface switches over to Data read or write,
because these functions are correlated to the address.
Also controlled by the address the CCU now transmits
eight or sixteen clock pulses, and accordingly one or two
bytes of data are written into the addressed IC or read
out from it, beginning with the LSB.
The INTERMETALL Bus (IM bus for short) was de-
signed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means that the CCU
acts as a master, whereas all controlled ICs have purely
slave status.
The IM bus consists of three lines for the signals Ident
(ID), Clock (DL) and Data (D). The clock frequency
range is 50 Hz to 1 MHz. Ident and clock are unidirec-
tional from the CCU to the slave ICs, Data is bidirection-
al. Bidirectionality is achieved by using open-drain out-
puts. The 2.5 to 1 kOhm pull-up resistor common to all
outputs must be connected externally.
The completion of the bus transaction is signalled by a
short Low state pulse of the ID signal. This initiates the
storing of the transferred data.
The timing of a complete IM bus transaction is shown in
Fig. 4–14. In the non-operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, and sets the CL signal to Low level as well
For future software compatibility, the CCU must write a
zero into all bits not currently used. When reading unde-
fined or unused bits, the CCU must adopt “don’t care”
behavior.
36
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
