128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Common Flash Interface
Primary Micron-Specific Extended Query
Table 49: Primary Micron-Specific Extended Query
Hex Offset
ASCII Value
(DQ[7:0])
P = 10Ah
Length Description
Address Hex Code
(P+0)h
(P+1)h
(P+2)h
3
Primary extended query table, unique ASCII
string: PRI
10A:
10B:
10C:
10D:
10E:
10F:
- -50
- -52
- -49
- -31
- -34
P
R
I
(P+3)h
(P+4)h
1
1
4
Major version number, ASCII
Minor version number, ASCII
1
4
–
(P+5)h
(P+6)h
(P+7)h
(P+8)h
Optional feature and command support (1 = yes;
0 = no)
Bits 10–31 are reserved; undefined bits are 0
If bit 31 = 1, then another 31-bit field of optional
features follows at the end of the bit 30 field
- -E6 (Non-
Mux)
- -66 (A/D
Mux)
110:
- -07
–
(90nm,
65nm)
111:
112:
- -00
- -00
–
–
Bit 0: Chip erase supported
Bit 0 = 0
No
Yes
Yes
No
No
Yes
Yes
Bit 1: Suspend erase supported
Bit 2: Suspend program supported
Bit 3: Legacy lock/unlock supported
Bit 4: Queued erase supported
Bit 5: Instant individual block locking supported
Bit 6: OTP bits supported
Bit 1 = 1
Bit 2 = 1
Bit 3 = 0
Bit 4 = 0
Bit 5 = 1
Bit 6 = 1
Bit 7 = 0
Bit 7: Page mode read supported
No: A/D Mux
Yes: Non-Mux
Bit 8: Synchronous read supported
Bit 9: Simultaneous operations supported
Bit 10: Reserved
Bit 8 = 1
Bit 9 = 1
Yes
Yes
No
No
No
–
BIt 10 = 0
Bit 30 = 0
Bit 31 = 0
Bit 30: CFI links to follow
Bit 31: another optional features field to follow.
(P+9)h
1
2
Supported functions after suspend: read array,
status, query
113:
- -01
Other supported options:
Bits 1–7 reserved; undefined bits are 0
Bit 0: Program supported after erase suspend
Bit 0 = 1
Yes
–
(P+A)h
(P+B)h
Block status register mask:
Bits 2 – 3 and 6 - 15 are reserved; undefined bits
are 0
114:
115:
- -33
(90nm,
65nm)
–
Bit 0: Block lock bit status register active
Bit 1: Block lock-down bit status active
Bit 0 = 1
Bit 1 = 1
Yes
Yes
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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