128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
Figure 25: Synchronous Continuous Misaligned Burst Read (A/D MUX)
Latency count
tCLK
tCH
tCL
CLK
A
A[MAX:16]
tCHQV
tCHQX
tAVCH tCHAX
A
tCHQV
A/DQ[15:0]
ADV#
Q
Q
End of WL
Q
tCHVL tVLCH tCHVH
tELCH
CE#
tCHGL
OE#
tCHTV
tGLTV
tGLTX
tCHTV
tCHTV
tCHTX
tCHTX
tGHTV
WAIT
RST#
1. 8-word and 16-word burst are always wrap-only.
Notes:
2. WAIT shown as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
3. tAVQV, tELQV, and tVLQV apply to legacy-latching only.
4. tACC and tVLVH apply to clock-latching only.
Figure 26: Synchronous Burst with Burst-Interrupt (AD-Mux)
t
Latency count
CLK
t
t
CH
CL
CLK
A
A
A[MAX:16]
t
CHQV
t
t
t
t
t
t
CHQX
AVCH CHAX
CHQV
AVCH CHAX
A/DQ[15:0]
A
A
Q
Q
t
t
t
t
t
t
CHVL VLCH CHVH
CHVL VLCH CHVH
ADV#
CE#
t
ELCH
t
ELCH
t
CHGL
OE#
t
CHTV
t
GLTV
GLTX
t
WAIT
RST#
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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