128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
Figure 21: Synchronous Continuous Misaligned Burst Read (Non-MUX)
Latency count
tCLK
tCH
tCL
CLK
tAVCH tCHAX
tVLCH tCHVH
A[MAX:0]
tCHVL
ADV#
tELCH
CE#
OE#
tGLTX
tGLTV
tCHTV
tCHTV
tCHTV
tCHTX
tCHTX
WAIT
tCHQV
tCHQV
tCHQX
DQ[15:0]
RST#
Q
Q
End of WL
1. WAIT shown as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
2. ADV# may be held LOW throughout the synchronous READ operation.
3. tAVQV, tELQV, and tVLQV apply to legacy-latching only.
Notes:
4. tACC and tVLVH apply to clock-latching only.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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