128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Write Specifications
8. When performing a READ STATUS operation following any command that alters the sta-
tus register, tWHGL is 20ns.
9. Add 10ns if the WRITE operation results in an RCR or block lock status change for the
subsequent READ operation to reflect this change.
10. Either tVHWL or tCHWL is required to meet the specification depending on the address
latching mechanism; both of these specifications can be ignored if the clock is not tog-
gling during the WRITE cycle.
11. If ADV# remains LOW after the WRITE cycle completes, a new READ cycle will start.
Figure 27: Write Timing
A[MAX:16]
tAVWH
tWHDX
tDVWH
D
tWHAX
A/DQ[15:0]
A
A
D
tAVVH
tVLVH
tAVVH
tVLVH
tVHAX
tWHVH
tVHAX
tVLWH
ADV#
CE#
tWHEH
tWHAV
tELWL
tELWL
tWHEH
tVHWL
tWLWH
tWHWL
tWLWH
WE#
OE#
tPHWL
RST#
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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