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PC28F128G18FF 参数 Datasheet PDF下载

PC28F128G18FF图片预览
型号: PC28F128G18FF
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB, 256MB,512MB ,1GB的StrataFlash存储器 [128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory]
分类和应用: 存储
文件页数/大小: 118 页 / 1154 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory  
AC Write Specifications  
AC Write Specifications  
Table 41: AC Write Specifications  
Notes 1 and 2 apply to all  
Parameter  
Symbol  
tPHWL  
tELWL  
Min  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Notes  
RST# HIGH recovery to WE# LOW  
CE# setup to WE# LOW  
150  
3
10  
4
0
WE# write pulse width LOW  
Data setup to WE# HIGH  
Address setup to WE# HIGH  
CE# hold from WE# HIGH  
Data hold from WE# HIGH  
Address hold from WE# HIGH  
WE# pulse width HIGH  
tWLWH  
tDVWH  
tAVWH  
tWHEH  
tWHDX  
tWHAX  
tWHWL  
tVPWH  
tQVVL  
40  
40  
40  
0
0
0
20  
5
VPP setup to WE# HIGH  
200  
3, 7  
3, 7  
3, 7  
3, 7  
8
VPP hold from status read  
WP# hold from status read  
WP# setup to WE# HIGH  
WE# HIGH to OE# LOW  
0
tQVBL  
0
tBHWH  
tWHGL  
tVLWH  
tWHQV  
200  
0
ADV# LOW to WE# HIGH  
WE# HIGH to read valid  
55  
tAVQV + 30  
3, 6, 9  
WRITE Operation to Asynchronous Read Transition  
WE# HIGH to address valid  
tWHAV  
Write to Synchronous Read Specification  
WE# HIGH to CLK HIGH @ 110 MHz  
WE# HIGH to CE# LOW  
tWHCH  
tWHEL  
tWHVL  
15  
9
ns  
ns  
ns  
3, 6, 11  
3, 6, 11  
3, 6, 11  
WE# HIGH to ADV# LOW  
7
Write Specifications with Clock Active  
ADV# HIGH to WE# LOW  
tVHWL  
tCHWL  
27  
27  
ns  
ns  
11  
11  
CLK HIGH to WE# LOW  
1. Write timing characteristics during erase suspend are the same as WRITE-only opera-  
tions.  
Notes:  
2. A WRITE operation can be terminated with either CE# or WE#.  
3. Sampled, not 100% tested.  
4. Write pulse width LOW (tWLWH or tELEH) is defined from CE# or WE# LOW (whichever  
occurs last) to CE# or WE# HIGH (whichever occurs first). Hence, tWLWH = tELEH = tWLEH  
= tELWH.  
5. Write pulse width HIGH (tWHWL or tEHEL) is defined from CE# or WE# HIGH (whichever  
occurs first) to CE# or WE# LOW (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL  
= tEHW.  
6. tWHCH must be met when transitioning from a WRITE cycle to a synchronous burst read.  
In addition CE# or ADV# must toggle when WE# goes HIGH.  
7. VPP and WP# must be at a valid level until erase or program success is determined.  
PDF: 09005aef8448483a  
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
73  
© 2011 Micron Technology, Inc. All rights reserved.  
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