128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
Figure 22: Synchronous Burst with Burst Interrupt Read (Non-MUX)
Latency count
tCLK
tCH
tCL
CLK
tAVCH tCHAX
tAVCH tCHAX
tVLCH
A[MAX:0]
tCHVL
tVHVL
tCHVL tVLCH tCHVH
tCHVH
ADV#
tELCH
tELCH
CE#
OE#
tGLTV
tGLTX
tCHTV
tCHQX
tCHTV
tCHTX
WAIT
tCHQV
tCHQV
tCHQX
DQ[15:0]
RST#
Q
Q
Q
1. WAIT shown as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
2. A burst can be interrupted by toggling CE# or ADV#.
Notes:
3. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown in this figure).
4. tAVQV, tELQV, and tVLQV apply to legacy-latching only.
5. tACC and tVLVH apply to clock-latching only.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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