128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
Table 40: AC Read Specifications (CLK-Latching, 133 MHz), VCCQ = 1.7V to 2.0V (Continued)
Note 1 applies to all parameters
96ns
Parameter
Symbol
Min
Max
Unit
Notes
CLK fall/rise time
tFCLK/RCLK
0.3
1.2
ns
Synchronous Specifications
Address setup to CLK HIGH
ADV# LOW setup to CLK HIGH
CE# LOW setup to CLK HIGH
CLK to output valid
tAVCH
tVLCH
tELCH
tCHQV
tCHQX
tCHAX
tCHTV
tCHVL
tCHTX
tCHVH
tCHGL
tACC
2
2
–
–
ns
ns
2.5
–
–
ns
5.5
–
ns
Output hold from CLK HIGH
Address hold from CLK HIGH
CLK HIGH to WAIT valid
2
ns
2
–
ns
–
5.5
–
ns
ADV# HIGH hold from CLK
WAIT hold from CLK
2
ns
2
–
ns
ADV# hold from CLK HIGH
CLK to OE# LOW (A/D MUX only)
Read access time from address latching clock
ADV# pulse width LOW for sync reads
ADV# HIGH to CLK HIGH
2
–
ns
4
2
–
ns
96
1
–
ns
tVLVH
tVHCH
2
clocks
ns
4
4
2
–
1. See Electrical Specifications – AC Characteristics and Operating Conditions for timing
measurements and MAX allowable input slew rate.
Notes:
2. OE# can be delayed by up to tELQV - tGLQV after the CE# falling edge without impact to
tELQV.
3. Sampled, not 100% tested.
4. For 45nm devices, these specifications are not required as a result of the enhanced CLK-
latching scheme. See the StrataFlash® Cellular Memory 65nm to 45nm M Family Migra-
tion Guide and the StrataFlash® Cellular Memory 65nm to 45nm M Family Latching
Scheme Migration Guide for more information.
AC Read Timing
The Synchronous read timing waveforms apply to both 108 and 133 MHz devices. How-
ever, devices that only support up to 108 MHz need not meet the following timing spec-
ifications.
t
• CHVH
t
• CHGL
t
• ACC
t
• VLVH
t
• VHCH
Note: The WAIT signal polarity in all the timing waveforms is low-true (RCR10 = 0).
WAIT is shown as de-asserted with valid data (RCR8 = 0). WAIT is de-asserted during
asynchronous reads.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
64
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