128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Read Specifications
AC Read Specifications
AC Read Specifications (CLK-Latching, 133 MHz)
Table 40: AC Read Specifications (CLK-Latching, 133 MHz), VCCQ = 1.7V to 2.0V
Note 1 applies to all parameters
96ns
Parameter
Symbol
Min
Max
Unit
Notes
Asynchronous Specifications
READ cycle time
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
96
–
–
96
96
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to output valid
CE# LOW to output valid
OE# LOW to output valid
RST# HIGH to output valid
CE# LOW to output in Low-Z
OE# LOW to output in Low-Z
CE# HIGH to output in High-Z
OE# HIGH to output in High-Z
–
–
2
–
150
–
0
0
–
3
2, 3
3
–
7
–
7
3
Output hold from first occurring address, CE#,
or OE# change
0
–
3
CE# pulse width HIGH
tEHEL
tELTV
tEHTZ
tGHTV
tGLTV
tGLTX
tGHTZ
7
–
–
–
–
0
0
–
8
ns
ns
ns
ns
ns
ns
ns
CE# LOW to WAIT valid
CE# HIGH to WAIT High-Z
OE# HIGH to WAIT valid (A/D MUX only)
OE# LOW to WAIT valid
7
3
5.5
5.5
–
OE# LOW to WAIT in Low-Z
OE# HIGH to WAIT in High-Z (non-MUX only)
Latching Specifications
Address setup to ADV# HIGH
CE# LOW to ADV# HIGH
3
3
7
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tVHGL
tAPA
5
7
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# LOW to output valid
ADV# pulse width LOW
–
96
–
7
ADV# pulse width HIGH
7
–
Address hold from ADV# HIGH
ADV# HIGH to OE# LOW (A/D MUX only)
Page address access (non-MUX only)
RST# HIGH to ADV# HIGH
Clock Specifications
5
–
2
–
–
15
–
tPHVH
30
CLK frequency
fCLK
tCLK
tCH/CL
–
133
–
MHz
ns
CLK period
7.5
0.45
CLK HIGH/LOW time
0.55
CLK
period
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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