128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Power and Reset Specifications
Figure 15: RESET Operation Waveforms
t
t
PLPH
PHQV
V
(A) Reset during
IH
RST#
read mode
V
IL
t
t
PLRH
PLRH
Abort
complete
PHQV
V
(B) Reset during
program or block erase
P1 £ P2
IH
RST#
RST#
VCC
V
IL
t
t
Abort
PHQV
complete
V
(C) Reset during
program or block erase
P1 ³ P2
IH
V
IL
t
VCCPH
(D) VCC power-up to
RST# HIGH
V
CC
0V
Table 32: Reset Specifications
Note 1 applies to all
Parameter
Symbol
Min
100
–
Max
–
Unit
ns
Notes
2, 3, 6
3, 6
RST# pulse width LOW
tPLPH
tPLRH
RST# LOW to device
reset during erase
25
µs
RST# LOW to device
reset during program
–
25
–
3, 6
4, 5
VCC power valid to RST# de-asser-
tion (HIGH)
tVCCPH
300
1. These specifications are valid for all packages and speeds, and are sampled, not 100%
tested.
2. The device might reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
Notes:
3. Not applicable if RST# is tied to VCCQ
4. If RST# is tied to the VCC supply, the device is not ready until tVCCPH after VCC ≥ VCC,min
5. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must
.
.
not exceed VCC until VCC ≥ VCC,min
.
6. Reset completes within tPLPH if RST# is asserted while no ERASE or PROGRAM operation
is executing.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
54
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