128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Block Lock
Table 27: BLOCK LOCK Command Bus Cycles (Continued)
Setup WRITE Cycle
Address Bus
Setup WRITE Cycle
Data Bus
Confirm WRITE Cycle
Address Bus
Confirm WRITE Cycle
Data Bus
Command
BLOCK
LOCK-
DOWN
Block address
0060h
Block address
002Fh
Table 28: Block Lock Configuration
Block Lock Configu-
ration
Block Base Address
Block base address = 0x02
Block base address = 0x02
Block base address = 0x02
Bit
Block is unlocked
Block is locked
DQ0 = 0b0
DQ0 = 0b1
DQ1 = 0b0
Block is not locked
down
Block is locked down
Block base address = 0x02
DQ1 = 0b1
Figure 12: BLOCK LOCK Operations
Locked
down
[0, 1, 1]
Hardware
locked
[0, 1, 1]
Locked
[X, 0, 1]
Power-Up
or
exit from reset
Software
locked
[1, 1, 1]
Unlocked
[X, 0, 0]
Unlocked
[1, 1, 0]
Software control (LOCK, UNLOCK, LOCK-DOWN command)
Hardware control (WP#)
1. The [n,n,n] denotes logical state of WP#, DQ1,and DQ0, respectively; X = "Don’t Care."
Notes:
2. The [0,1,1] states should be tracked by system software to differentiate between the
hardware-locked state and the lock-down state.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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