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PC28F128G18FF 参数 Datasheet PDF下载

PC28F128G18FF图片预览
型号: PC28F128G18FF
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB, 256MB,512MB ,1GB的StrataFlash存储器 [128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory]
分类和应用: 存储
文件页数/大小: 118 页 / 1154 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory  
One-Time Programmable Operations  
One-Time Programmable Operations  
The device contains sixteen 128-bit one-time programmable (OTP) blocks, two 64-bit  
OTP blocks, and two 16-bit OTP lock registers. OTP lock register 0 is used for locking  
OTP blocks 0 and 1 (two 64-bit blocks), and OTP lock register 1 is used for locking OTP  
blocks 2 through 17 (sixteen 128-bit blocks).  
Each block contains OTP bits that are factory set to 1 and can only be programmed from  
1 to 0; OTP block bits cannot be erased from 0 back to 1. This feature makes the OTP  
blocks particularly useful for implementing system-level security schemes, permanent-  
ly storing data, or storing fixed system parameters.  
OTP block 0 is pre-programmed with a unique 64-bit value and locked at the factory.  
OTP block 1 contains all 1s and is user-programmable. OTP blocks 1 through 16 contain  
all 1s and are user-programmable.  
Each OTP block can be accessed multiple times to program individual bits, as long as  
the block remains unlocked. When a lock register bit is programmed, the associated  
OTP block can only be read—it can no longer be programmed.  
OTP lock register bits lock out subsequent programming of the corresponding OTP  
block. Each OTP block can be locked by programming its corresponding lock bit to 0. As  
long as an OTP block remains unlocked (that is, its lock bit = 1), any of its remaining 1  
bits can be programmed to 0.  
Note: Once an OTP block is locked, it cannot be unlocked. Attempts to program a  
locked OTP block will fail with error bits set. Additionally, because the lock register bits  
themselves are OTP, when programmed, lock register bits cannot be erased. Therefore,  
when an OTP block is locked, it cannot be unlocked.  
Table 29: Program OTP Area Command Bus Cycles  
Setup WRITE Cycle  
Address Bus  
Device address  
Setup WRITE Cycle Confirm WRITE Cycle Confirm WRITE Cycle  
Command  
Data Bus  
Address Bus  
Data Bus  
PROGRAM OTP AREA  
00C0h  
OTP register address  
Register data  
PDF: 09005aef8448483a  
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2011 Micron Technology, Inc. All rights reserved.