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PC28F128G18FF 参数 Datasheet PDF下载

PC28F128G18FF图片预览
型号: PC28F128G18FF
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB, 256MB,512MB ,1GB的StrataFlash存储器 [128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory]
分类和应用: 存储
文件页数/大小: 118 页 / 1154 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory  
Erase Operations  
Erase Operations  
BLOCK ERASE  
Erasing a block changes 0s to 1s. To change 1s to 0s, a PROGRAM operation must be  
performed. Erasing is performed on a block basis; an entire block is erased each time an  
erase command sequence is issued. Once a block is fully erased, all addressable loca-  
tions within that block read as logical 1s (FFFFh).  
Only one BLOCK ERASE operation can occur at a time. A BLOCK ERASE operation is  
not permitted during program suspend. All BLOCK ERASE operations require the ad-  
dressed block to be unlocked, and VPP must be at VPPL or VPPH throughout the BLOCK  
ERASE operation. Otherwise, the operation aborts, setting the appropriate status regis-  
ter error bit(s).  
To perform a BLOCK ERASE operation, issue the BLOCK ERASE SETUP command at the  
desired block address. The read mode of the addressed partition automatically changes  
to read status register mode and remains in effect until another READ MODE command  
is issued.  
The ERASE CONFIRM command latches the address of the block to be erased. The ad-  
dressed block is preconditioned (programmed to all 0s), erased, and then verified.  
Issuing the READ STATUS REGISTER command to another partition switches that par-  
tition’s read mode to the read status register, thereby allowing block erase progress to be  
monitored from that partition’s address. SR0 indicates whether the addressed partition  
or the other partition is erasing.  
During a BLOCK ERASE operation, the status register indicates a busy status (SR[7] = 0).  
Issuing the READ ARRAY command to a partition that is actively erasing a main block  
causes subsequent reads from that partition to output invalid data. Valid array data is  
output only after the BLOCK ERASE operation has finished.  
Upon completion, the status register indicates a ready status (SR[7] = 1). The status reg-  
ister should be checked for any errors, and then cleared.  
If the device is deselected during an ERASE operation, the device continues to consume  
active power until the ERASE operation is completed.  
Asserting RST# immediately aborts the BLOCK ERASE operation, and array contents at  
the addressed location are indeterminate. The addressed block should be erased again.  
The only valid commands during a BLOCK ERASE operation are READ ARRAY, READ ID,  
READ CFI, and ERASE SUSPEND. After the BLOCK ERASE operation has completed,  
any valid command can be issued.  
Table 23: ERASE Command Bus Cycle  
Setup WRITE Cycle  
Setup WRITE Cycle Confirm WRITE Cycle Confirm WRITE Cycle  
Command  
Address Bus  
Data Bus  
Address Bus  
Data Bus  
BLOCK ERASE  
Device address  
0020h  
Block address  
00D0h  
PDF: 09005aef8448483a  
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2011 Micron Technology, Inc. All rights reserved.