128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Program Operations
Table 22: BEFP Requirements and Considerations
BEFP Requirements
Temperature (TCASE) must be 25 °C, ± 5 °C
Voltage on VCC must be within the allowable operating range
Voltage on VPP must be within the allowable operating range
Block being programmed must be erased and unlocked
BEFP Considerations Block cycling below 100 erase cycles
Reading from another partition during EFP (RWW) is not allowed
BEFP programs within one block at a time
BEFP cannot be suspended
BEFP Setup Phase
Issuing the BEFP SETUP and CONFIRM command sequence starts the BEFP algorithm.
The read mode of the addressed partition is automatically changed to read status regis-
ter mode.
The address used when issuing the SETUP and CONFIRM commands must be buffer-
size aligned within the block being programmed; buffer contents cannot cross block
boundaries.
Note: The READ STATUS REGISTER command must not be issued; it will be interpreted
as data to be written to the write buffer.
A setup delay (tBEFP/setup) occurs while the internal algorithm checks VPP and block
lock status. If errors are detected, the appropriate status register error bits are set and
the operation aborts.
The status register should be polled for successful BEFP setup, indicated by SR[7:0] = 0
(device busy, buffer ready for data).
BEFP Program/Verify Phase
Data is first written into the write buffer, then programmed into the array. During the
buffer fill sequence, the address used must be buffer-size aligned. Use of any other ad-
dress will cause the operation to abort with a program fail error, and any data previously
loaded in the buffer will not be programmed into the array.
The buffer fill data is stored in sequential buffer locations starting at address 00h. A
word count equal to the maximum buffer size is used; therefore, the buffer must be
completely filled. If the amount of data is less than the maximum buffer size, the re-
maining buffer locations must be padded with FFFFh to completely fill the buffer.
Array programming starts as soon as the write buffer is full. Data words from the write
buffer are programmed into sequential array locations. SR0 = 1 indicates the write buf-
fer is not available while the BEFP algorithm programs the array.
The status register should be polled for SR0 = 0 (buffer ready for data) to determine
when the array programming has completed and the write buffer is again available for
loading. The internal address is automatically incremented to enable subsequent array
programming to continue from where the previous buffer-fill/array program sequence
ended within the block. This cycle can be repeated to program the entire block.
BEFP Exit Phase
To exit the program/verify phase, write FFFFh to an address outside of the block.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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