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PC28F00BP30EFA 参数 Datasheet PDF下载

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型号: PC28F00BP30EFA
PDF下载: 下载PDF文件 查看货源
内容描述: Numonyx® Axcellâ ?? ¢ P30-65nm闪存 [Numonyx® Axcell™ P30-65nm Flash Memory]
分类和应用: 闪存内存集成电路
文件页数/大小: 86 页 / 11765 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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P30-65nm  
Table 26: AC Write Specifications (Sheet 2 of 2)  
Num  
Symbol  
Parameter  
Min  
Max  
Unit  
Notes  
Write to Synchronous Read Specifications  
W19  
W20  
W28  
t
t
t
WE# high to Clock valid  
19  
19  
7
-
-
-
ns  
ns  
ns  
1,2,3,6,10  
WHCH/L  
WHVH  
WHVL  
WE# high to ADV# high  
WE# high to ADV# low  
1,2,3,6,10,12  
Write Specifications with Clock Active  
W21  
W22  
t
t
ADV# high to WE# low  
Clock high to WE# low  
-
-
20  
20  
ns  
ns  
1,2,3,11,12  
1,2,3,11  
VHWL  
CHWL  
Notes:  
1.  
2.  
3.  
4.  
Write timing characteristics during erase suspend are the same as write-only operations.  
A write operation can be terminated with either CE# or WE#.  
Sampled, not 100% tested.  
Write pulse width low (t  
or t  
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high  
WLWH  
ELEH  
WLWH  
(whichever occurs first). Hence, t  
= t  
= t  
= t  
.
ELWH  
ELEH  
WLEH  
5.  
Write pulse width high (t  
or t  
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low  
WHWL  
EHEL  
(whichever occurs last). Hence, t  
= t  
= t  
= t  
).  
EHWL  
WHWL  
EHEL  
WHEL  
6.  
7.  
8.  
t
or t  
must be met when transiting from a write cycle to a synchronous burst read.  
WHVH  
WHCH/L  
VPP and WP# should be at a valid level until erase or program success is determined.  
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20  
for synchronous read.  
9.  
10.  
When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.  
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to  
reflect this change.  
11.  
These specs are required only when the device is in a synchronous mode and clock is active during address setup  
phase.  
12.  
13.  
These specs are required only when ADV# is used to latch address.  
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation  
to this timing specification.  
Figure 24: Write-to-Write Timing  
W5  
W8  
W5  
W8  
Address[A]  
W2  
W6  
W2  
W6  
CE# [E]  
W3  
W9  
W3  
WE# [W]  
OE# [G]  
W4  
W7  
W4  
W7  
Data [D/Q]  
W1  
RST# [P]  
Datasheet  
56  
Sept 2012  
Order Number: 208042-06  
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