P30-65nm
Table 25: AC Read Specifications - (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
(5)
Synchronous Specifications (Easy BGA)
R301
R302
R303
R304
R305
R306
R307
R311
R312
t
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
9
9
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVCH/L
t
VLCH/L
ELCH/L
t
9
-
1,6
t
/t
-
17
-
CHQV CLQV
t
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
CHQX
t
10
-
-
1,4,6
1,6
1
CHAX
t
t
t
17
-
CHTV
CHVL
CHTX
CLK valid to ADV# Setup
WAIT hold from CLK
3
3
-
1,6
Notes:
1.
See Figure 15, “AC Input/Output Reference Waveform” on page 49 for timing measurements and max
allowable input slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to t
Sampled, not 100% tested.
– t
after CE#’s falling edge without impact to t
ELQV
GLQV ELQV.
Address hold in synchronous burst read mode is t
or t
, whichever timing specification is satisfied first.
VHAX
CHAX
Synchronous burst read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
Figure 18: Asynchronous Single-Word Read (ADV# Low)
R1
R2
Address[A]
ADV#[V]
R3
R8
CE# [E]
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
Datasheet
52
Sept 2012
Order Number: 208042-06
MICRON [ MICRON TECHNOLOGY ]
