P30-65nm
Figure 27: Synchronous Read-to-Write Timing (Easy BGA)
LatencyCount
R301
R302
R306
CLK [C]
R2
W5
R101
W18
Address[A]
R105
R102
R106
R104
ADV# [V]
R303
R11
R3
R13
W6
CE# [E]
OE# [G]
R4
R8
W21
W22
W15
W21
W22
W2
W8
W3
W9
WE#[W]
WAIT [T]
R16
R307
R304
R312
R7
R305
W7
Q
D
D
Data [D/Q]
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low). Clock is
ignored during write operation.
Figure 28: Write-to-Synchronous Read Timing (Easy BGA)
Latency Count
R302
R301
R2
CLK[C]
W5
W8
R306
R106
Address[A]
ADV#[V]
R104
R303
W6
W2
R11
CE# [E]
W18
W19
W20
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R15
R3
R307
W7
R304
R305
R304
W4
D
Q
Q
Data [D/Q]
RST# [P]
W1
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low).
Datasheet
58
Sept 2012
Order Number: 208042-06
MICRON [ MICRON TECHNOLOGY ]
