P30-65nm
Figure 19: Asynchronous Single-Word Read for Easy BGA (ADV# Latch)
R1
R2
Address[A]
A[4:1][A]
R101
R105
R106
ADV#[V]
CE# [E]
R3
R8
R4
R9
OE# [G]
WAIT [T]
R15
R17
R7
R6
R10
Data [D/Q]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 20: Asynchronous Page-Mode Read Timing for Easy BGA
R2
A[Max:5] [A]
A[4:1]
Valid Address
R10
R10
R10
R10
0
1
2
F
R101
R105
R106
ADV#[V]
CE# [E]
R3
R8
R4
R9
OE# [G]
WAIT [T]
R6
R108
Q2
R108
Q3
R108
Q16
R13
DATA[D/Q]
Q1
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
53
Sept 2012
OrderNumber:208042-06