P30-65nm
15.3
AC Read Specifications
Table 25: AC Read Specifications - (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
512-Mbit/1-Gbit
2-Gbit
100
-
-
Easy BGA
R1
R2
R3
t
Read cycle time
105
ns
ns
ns
AVAV
TSOP
Easy BGA
TSOP
512-Mbit/1-Gbit
512-Mbit/1-Gbit
2-Gbit
110
-
-
100
105
110
100
105
110
25
150
-
t
Address to output valid
CE# low to output valid
-
-
AVQV
512-Mbit/1-Gbit
512-Mbit/1-Gbit
2-Gbit
-
-
Easy BGA
TSOP
t
-
ELQV
512-Mbit/1-Gbit
-
R4
R5
t
t
OE# low to output valid
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1
GLQV
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
-
PHQV
R6
t
0
0
-
1,3
1,2,3
ELQX
GLQX
EHQZ
GHQZ
R7
t
t
-
R8
20
15
-
R9
t
-
1,3
R10
R11
R12
R13
R15
R16
R17
t
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
0
17
-
OH
t
-
EHEL
1
t
CE# low to WAIT valid
17
20
17
-
ELTV
t
CE# high to WAIT high-Z
-
1,3
1
EHTZ
t
t
OE# low to WAIT valid
-
GLTV
GLTX
OE# low to WAIT in low-Z
0
-
1,3
t
OE# high to WAIT in high-Z
20
GHTZ
Latching Specifications (Easy BGA)
R101
R102
t
Address setup to ADV# high
CE# low to ADV# high
10
10
-
-
-
ns
ns
AVVH
t
ELVH
512-Mbit/1-Gbit
2-Gbit
100
105
110
-
Easy BGA
TSOP
R103
t
ADV# low to output valid
-
ns
1
VLQV
512-Mbit/1-Gbit
-
R104
R105
R106
R108
R111
t
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
10
10
9
ns
ns
ns
ns
ns
VLVH
VHVL
VHAX
t
-
t
-
1,4
1
t
-
25
-
APA
t
RST# high to ADV# high
30
PHVH
Clock Specifications (Easy BGA)
R200
R201
R202
R203
f
CLK frequency
CLK period
-
19.2
5
52
-
MHz
ns
CLK
CLK
t
1,3,5,6
t
CLK high/low time
CLK fall/rise time
-
ns
CH/CL
FCLK/RCLK
t
0.3
3
ns
Datasheet
51
Sept 2012
OrderNumber:208042-06
MICRON [ MICRON TECHNOLOGY ]
