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N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Serial Peripheral Interface Modes  
Serial Peripheral Interface Modes  
The device can be driven by a microcontroller while its serial peripheral interface is in  
either of the two modes shown here. The difference between the two modes is the clock  
polarity when the bus master is in standby mode and not transferring data. Input data is  
latched in on the rising edge of the clock, and output data is available from the falling  
edge of the clock.  
Table 7: SPI Modes  
Note 1 applies to the entire table  
SPI Modes  
Clock Polarity  
CPOL = 0, CPHA = 0  
CPOL = 1, CPHA = 1  
C remains at 0 for (CPOL = 0, CPHA = 0)  
C remains at 1 for (CPOL = 1, CPHA = 1)  
1. The listed SPI modes are supported in extended, dual, and quad SPI protocols.  
Note:  
Shown below is an example of three memory devices in extended SPI protocol in a sim-  
ple connection to an MCU on an SPI bus. Because only one device is selected at a time,  
that one device drives DQ1, while the other devices are High-Z.  
Resistors ensure the device is not selected if the bus master leaves S# High-Z. The bus  
master might enter a state in which all input/output is High-Z simultaneously, such as  
when the bus master is reset. Therefore, the serial clock must be connected to an exter-  
nal pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW.  
This ensures that S# and the serial clock are not HIGH simultaneously and that tSHCH  
is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp =  
parasitic capacitance of the bus line), is shorter than the time the bus master leaves the  
SPI bus in High-Z.  
Example: Cp = 50pF, that is R × Cp = 5μs. The application must ensure that the bus mas-  
ter never leaves the SPI bus High-Z for a time period shorter than 5μs. W# and HOLD#  
should be driven either HIGH or LOW, as appropriate.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
15  
© 2011 Micron Technology, Inc. All rights reserved.  
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