欢迎访问ic37.com |
会员登录 免费注册
发布采购

N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号N25Q512A13GF840E的Datasheet PDF文件第9页浏览型号N25Q512A13GF840E的Datasheet PDF文件第10页浏览型号N25Q512A13GF840E的Datasheet PDF文件第11页浏览型号N25Q512A13GF840E的Datasheet PDF文件第12页浏览型号N25Q512A13GF840E的Datasheet PDF文件第14页浏览型号N25Q512A13GF840E的Datasheet PDF文件第15页浏览型号N25Q512A13GF840E的Datasheet PDF文件第16页浏览型号N25Q512A13GF840E的Datasheet PDF文件第17页  
512Mb, Multiple I/O Serial Flash Memory  
Device Protection  
Device Protection  
Table 3: Data Protection Using Device Protocols  
Note 1 applies to the entire table  
Protection by:  
Description  
Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is out-  
side the operating specification.  
Command execution check  
Ensures that the number of clock pulses is a multiple of one byte before executing a  
PROGRAM or ERASE command, or any command that writes to the device registers.  
WRITE ENABLE operation  
Ensures that commands modifying device data must be preceded by a WRITE ENABLE  
command, which sets the write enable latch bit in the status register.  
1. Extended, dual, and quad SPI protocol functionality ensures that device data is protec-  
ted from excessive noise.  
Note:  
Table 4: Memory Sector Protection Truth Table  
Note 1 applies to the entire table  
Sector Lock Register  
Sector Lock  
Down Bit  
Sector Write Lock  
Bit  
Memory Sector Protection Status  
0
0
1
1
0
1
0
1
Sector unprotected from PROGRAM and ERASE operations. Protection status re-  
versible.  
Sector protected from PROGRAM and ERASE operations. Protection status rever-  
sible.  
Sector unprotected from PROGRAM and ERASE operations. Protection status not  
reversible except by power cycle or reset.  
Sector protected from PROGRAM and ERASE operations. Protection status not  
reversible except by power cycle or reset.  
1. Sector lock register bits are written to when the WRITE TO LOCK REGISTER command is  
executed. The command will not execute unless the sector lock down bit is cleared (see  
the WRITE TO LOCK REGISTER command).  
Note:  
Table 5: Protected Area Sizes – Upper Area  
Note 1 applies to the entire table  
Status Register Content  
Memory Content  
Top/  
Bottom  
Bit  
BP3  
0
BP2  
0
BP1  
0
BP0  
0
Protected Area  
Unprotected Area  
All sectors  
0
None  
0
0
0
0
1
Sector 1023  
Sectors (0 to 1022)  
Sectors (0 to 1021)  
Sectors (0 to 1019)  
Sectors (0 to 1015)  
Sectors (0 to 1007)  
0
0
0
1
0
Sectors (1022 to 1023)  
Sectors (1020 to 1023)  
Sectors (1016 to 1023)  
Sectors (1008 to 1023)  
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
13  
© 2011 Micron Technology, Inc. All rights reserved.  
 复制成功!