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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Protection modes  
N25Q128 - 1.8 V  
7
Protection modes  
There are protocol-related and specific hardware and software protection modes. They are  
described below.  
7.1  
SPI Protocol-related protections  
This applies to all three protocols. The environments where non-volatile memory devices  
are used can be very noisy. No SPI device can operate correctly in the presence of  
excessive noise. To help combat this, the N25Q128 features the following data protection  
mechanisms:  
„
Power On Reset and an internal timer (tPUW) can provide protection against  
inadvertent changes while the power supply is outside the operating specification.  
„
Program, Erase, and Write Status Register instructions are checked to ensure the  
instruction includes a number of clock pulses that is a multiple of a byte before they are  
accepted for execution.  
„
All instructions that modify data must be preceded by a Write Enable (WREN)  
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state  
by the following events (in Extended SPI protocol mode):  
Power-up  
Write Disable (WRDI) instruction completion  
Write Status Register (WRSR) instruction completion  
Write to Lock Register (WRLR) instruction completion  
Program OTP (POTP) instruction completion  
Page Program (PP) instruction completion  
Dual Input Fast Program (DIFP) instruction completion  
Dual Input Extended Fast Program (DIEFP) instruction completion  
Quad Input Fast Program (QIFP) instruction completion  
Quad Input Extended Fast Program (QIEFP) instruction completion  
Subsector Erase (SSE) instruction completion  
Sector Erase (SE) instruction completion  
Bulk Erase (BE) instruction completion  
This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIO-  
SPI protocol modes.  
7.2  
Specific hardware and software protection  
There are two software protected modes, SPM1 and SPM2, that can be combined to protect  
the memory array as required. The SPM2 can be locked by hardware with the help of the W  
input pin.  
SPM1  
The first software protected mode (SPM1) is managed by specific Lock Registers assigned  
to each 64 Kbyte sector.  
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