N25Q128 - 1.8 V
Volatile and Non Volatile Registers
The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is as soon as the
Program/Erase Suspend command (PES) has been issued, therefore the device may still
complete the operation before entering the Suspend Mode.
The Program Suspend Status should be considered valid when the P/E Controller bit is high
(FSR<7>=1).
When a Program/Erase Resume command (PER) is issued the Program Suspend Status bit
returns Low (FSR<2>=0)
6.5.7
Protection Status bit
The bit 1 of the Flag Status Register represents the Protection Status bit. It indicates that an
Erase or Program operation has tried to modify the contents of a protected array sector, or
that a modify operation has tried to access to a locked OTP space. The Protection Status bit
is related to all possible protection violations as follows:
The sector is protected by Software Protection Mode 1 (SPM1) Lock registers,
The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits
(standard SPI Status Register),
An attempt to program OTP when locked,
A Write Status Register command (WRSR) on STD SPI Status Register when locked by
the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware Protection
Mode).
Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag
Status Register command (CLFSR). If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
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