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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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N25Q128 - 1.8 V  
Volatile and Non Volatile Registers  
6.4.3  
Reset/Hold disable VECR<4>  
The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the  
Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register  
(WVECR) instruction. This feature can be useful to avoid accidental Hold or Reset condition  
entries in applications that never require the Hold (Reset) functionality. If this bit is set to 0  
the Hold (Reset) functionality is disabled, it is possible to enable it back by setting this bit to  
1.  
Please note that after the next power on the Hold (Reset) functionality will be enabled again  
unless the bit 4 of the Non Volatile Configuration Register is set to 0.  
Note:  
Reset functionality is available instead of Hold in devices with a dedicated part number. See  
Section 16: Ordering information.  
6.4.4  
Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3>  
The bit 3 of the Volatile Enhanced Configuration Register determines whether it is possible  
to use the Vpp accelerating voltage to speed up the internal modify operation with the Quad  
program and erase instructions (both in Extended or QIO-SPI protocols).  
To use the Vpp voltage with the Quad I/O modify instructions, this bit must be set to 0. The  
default value is 1, in which case the Vpp pin functionality is disabled in all Quad I/O  
operations: both in Extended SPI and QIO-SPI protocols.  
If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol,  
after a Quad Command Page Program instruction or an Erase instruction is received (with  
all input data in the Program case) and the memory is de-selected, the protocol temporarily  
switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value (this  
transition is mandatory to come back to QIO-SPI protocol), to enable the possibility to  
perform polling instructions (to check if the internal modify cycle is finished by means of the  
WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status  
register) or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in  
his Vpp functionality.  
If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify  
instruction (both in Extended SPI protocol and QIO-SPI protocol), there is a maximum  
allowed time-out of 200 ms after the last instruction input is received and the memory is de-  
selected to raise the Vpp signal to Vpph; otherwise, the modify instruction starts at normal  
speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit  
3.  
6.4.5  
Output Driver Strength VECR<2:0>  
The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to  
optimize the impedance at Vcc/2 output voltage for the specific application as described in  
Table 7.: Volatile Enhanced Configuration Register.  
The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile  
Configuration Register (NVCR), the parts are delivered with the output impedance at Vcc/2  
equal to 30 Ohms.  
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