Instructions
N25Q128 - 1.8 V
Figure 82. Program OTP instruction sequence QIO-SPI
S
14
9 10 11 12 13
0
1
2
3
4
5
6
7
8
C
Data
byte1 byte2
Data
Data
Instruction
24-Bit Address
byten
DQ0
DQ1
4
5
6
0
1
2
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11
4
5
6
7
0
4
0
4
0
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
DQ2
DQ3
7
3
Quad_Program_OTP
9.3.8
Subsector Erase (SSE)
For devices with a dedicated part number, at the bottom (or top) of the addressable area
there are 8 boot sectors, each one having 16 4Kbytes subsectors. (See Section 16:
Ordering information.) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside
the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must
previously have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol, please refer to Section 9.1.17: Subsector
Erase (SSE) for further details.
142/185
MICRON [ MICRON TECHNOLOGY ]
