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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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N25Q128 - 1.8 V  
Instructions  
9.3.5  
Write Disable (WRDI)  
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.  
Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and  
DQ3, the instruction functionality is exactly the same as the Write Disable (WRDI)  
instruction of the Extended SPI protocol, please refer to Section 9.1.10: Write Disable  
(WRDI) for further details.  
Figure 78. Write Disable instruction sequence QIO-SPI  
S
0
1
C
Instruction  
DQ0  
DQ1  
DQ2  
DQ3  
Quad_Write_Disable  
9.3.6  
Quad Command Page Program (QCPP)  
The Quad Command Page Program (QCPP) instruction allows to program the memory  
content in DIO-SPI protocol, parallelizing the instruction code, the address and the input  
data on four pins (DQ0, DQ1, DQ2 and DQ3). Before it can be accepted, a Write Enable  
(WREN) instruction must previously have been executed. The Quad Command Page  
Program (QCPP) instruction can be issued, when the device is set in QIO-SPI mode, by  
sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the  
effect is exactly the same. The 3 instruction codes are all accepted to help the application  
code porting from Extended SPI protocol to QIO-SPI protocol.  
Apart for the parallelizing on four pins of the instruction code, the Quad Command Page  
Program instruction functionality is exactly the same as the Quad Input Extended Fast  
Program of the Extended SPI protocol, please refer to Section 9.1.15: Quad Input Extended  
Fast Program for further details.  
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