N25Q128 - 1.8 V
Instructions
Figure 83. Subsector Erase instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9
C
Instruction
24-Bit Address
DQ0
20 16 12
21 17 13
8
9
4
5
6
7
0
DQ1
DQ2
DQ3
1
2
22 18 14 10
23 19 15 11
3
Quad_Subsector_Erase
9.3.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase
(SE) instruction of the Extended SPI protocol, please refer to Section 9.1.18: Sector Erase
(SE) for further details.
Figure 84. Sector Erase instruction sequence QIO-SPI
S
0
1
2
3
4
5
6
7
8
9
C
Instruction
24-Bit Address
DQ0
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11
4
5
6
7
0
DQ1
DQ2
DQ3
1
2
3
Quad_Sector_Erase
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