Instructions
N25Q128 - 1.8 V
Figure 52. Program OTP instruction sequence DIO-SPI
S
C
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Instruction
24-Bit Address
DataByte1
DataByten
DataByte2
6
7
4
5
2
3
0
1
6
4
0
6
4
0
22 20 18 16
23 21 19 17
6
4
0
14 12 10
8
2
2
2
DQ0
DQ1
7
5
1
7
5
1
7
5
1
3
15 13 11
9
3
3
Dual_Program_OTP
9.2.8
Subsector Erase (SSE)
For devices with bottom or top architecture, at the bottom (or top) of the addressable area
there are 8 boot sectors, each one having 16 4Kbytes subsectors. The Subsector Erase
(SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the address on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Subsector Erase (SSE)
instruction of the Extended SPI protocol, please refer to Section 9.1.17: Subsector Erase
(SSE) for further details.
Figure 53. Subsector Erase instruction sequence DIO-SPI
S
C
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
24-Bit Address
14 12 10 8
6
7
4
5
2
3
0
1
22 20 18 16
23 21 19 17
DQ0
DQ1
15 13 11 9
Dual_Subsector_Erase
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