N25Q128 - 1.8 V
Instructions
The Write Volatile Enhanced Configuration register (WRVECR) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data
input (DQ0).
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Volatile Enhanced Configuration register (WRVECR) instruction is not
executed.
When the new data are latched, the write enable latch (WEL) is reset.
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows the user to
change the values of all the Volatile Enhanced Configuration Register bits, described in
Table 7.: Volatile Enhanced Configuration Register.
The Write Volatile Enhanced Configuration Register impacts the memory behavior right after
the instruction is received by the device.
Figure 41. Write Volatile Enhanced Configuration Register instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
VECR In
7
6
5
4
3
2
0
1
DQ0
DQ1
High Impedance
MSB
Write_VECR
9.1.34
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from I
to
CC1
I
, as specified in Table 32).
CC2
To take the device out of Deep Power-down mode, the Release from Deep Power-down
(RDP) instruction must be issued. No other instruction must be issued while the device is in
Deep Power-down mode.
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