4 MEG x 4
FPM DRAM
SELF REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS#
t
RPC
t
t
t
t
t
t
CHR
RPC
CP
CSR
CHR
CSR
V
V
IH
IL
CAS#
Q
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE#
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
15
MAX
MIN
15
MAX
UNITS
ns
SYMBOL
MIN
MAX
MIN
5
MAX
UNITS
ns
t
t
CHD
RPC
5
90
8
t
t
CP
8
10
ns
RPS
105
10
ns
t
t
CSR
5
5
ns
WRH
ns
t
t
RASS
100
30
100
40
µs
WRP
8
10
ns
t
RP
ns
t
NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
t
2. Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2000, Micron Technology, Inc.
18
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