4 MEG x 4
FPM DRAM
1
HIDDEN REFRESH CYCLE
(WE# = HIGH; OE# = LOW)
t
t
t
RAS
RAS
RP
V
V
IH
IL
RAS#
t
t
t
t
CRP
RCD
RSH
CHR
V
V
IH
IL
CASL#/CASH#
t
t
AR
RAD
t
t
t
t
CAH
ASR
RAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
t
AA
t
t
t
RAC
CAC
CLZ
t
OFF
V
V
IOH
IOL
DQx
OE#
OPEN
VALID DATA
OPEN
t
OE
t
OD
t
ORD
V
IH
V
IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
12
MIN
MAX
15
UNITS
ns
t
t
AA
25
30
OE
t
t
AR
38
0
45
0
ns
OFF
0
0
12
0
0
15
ns
t
t
ASC
ns
ORD
ns
t
t
ASR
0
0
ns
RAC
50
60
ns
t
t
CAC
13
15
ns
RAD
9
12
10
60
14
40
15
ns
t
t
CAH
8
8
0
5
0
10
10
0
ns
RAH
9
ns
t
t
CHR
ns
RAS
50
11
30
13
10,000
10,000
ns
t
t
CLZ
ns
RCD
ns
t
t
CRP
5
ns
RP
ns
t
t
OD
12
0
15
ns
RSH
ns
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2000, Micron Technology, Inc.
17
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