256Mb: x4, x8, x16 SDRAM
READ Operation
Figure 28: Alternating Bank Read Accesses
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
Command
DQM
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
t
AS
t
AH
Row
Row
Row
Row
Column m
Column b1
Address
t
t
AH
AS
Enable auto precharge
Enable auto precharge
Row
Row
A10
t
AS
t
AH
Bank 0
Bank 0
Bank 3
Bank 3
BA0, BA1
Bank 0
t
AC
t
t
t
t
AC
OH
AC
OH
AC
OH
AC
OH
t
t
t
t
t
t
OH
AC
D
D
D
D
D
OUT
DQ
OUT
OUT
OUT
OUT
t
LZ
t
t
t
t
t
t
RP - bank 0
CL - bank 0
RCD - bank 0
Undefined
RCD - bank 0
RAS - bank 0
RC - bank 0
RRD
t
CL - bank 3
Don’t Care
RCD - bank 3
1. For this example, BL = 4 and CL = 2.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
56
© 1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
