256Mb: x4, x8, x16 SDRAM
READ Operation
Figure 25: READ-to-WRITE With Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
READ
NOP
NOP
NOP
NOP
WRITE
Command
Address
Bank,
Col n
Bank,
Col b
t
HZ
D
D
OUT
IN
DQ
t
DS
Transitioning data
Don’t Care
1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank.
Note:
Figure 26: READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
PRECHARGE
Command
Address
DQ
X = 1 cycle
Bank
a or all)
Bank
Col
a
n
,
Bank
a,
(
Row
DOUT
DOUT
DOUT
DOUT
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
Bank
NOP
X = 2 cycles
NOP
ACTIVE
Command
Address
DQ
Bank
Col
a,
Bank
a,
(a or all)
Row
DOUT
DOUT
DOUT
DOUT
CL = 3
Transitioning data
Don’t Care
1. DQM is LOW.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
54
© 1999 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
