256Mb: x4, x8, x16 SDRAM
READ Operation
Figure 23: Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
Command
Address
DQ
READ
READ
READ
READ
NOP
NOP
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
DOUT
DOUT
DOUT
DOUT
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
Command
Address
DQ
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
DOUT
DOUT
DOUT
DOUT
CL = 3
Transitioning data
Don’t Care
1. Each READ command can be issued to any bank. DQM is LOW.
Note:
Data from any READ burst can be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst can be followed immediately by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst can be ini-
tiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there is a possibility that the device driving the input data will go Low-Z before
the DQ go High-Z. In this case, at least a single-cycle delay should occur between the
last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 24 (page 53) and
Figure 25 (page 54). The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress da-
ta-out from the READ. After the WRITE command is registered, the DQ will go to High-Z
(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was
active on the clock just prior to the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was
LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6
would be invalid.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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52
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