256Mb: x4, x8, x16 SDRAM
READ Operation
Figure 22: Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
Command
X = 1 cycle
Bank,
Col n
Bank,
Col b
Address
DQ
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Command
X = 2 cycles
Bank,
Col n
Bank,
Col b
Address
DQ
DOUT
DOUT
DOUT
DOUT
DOUT
CL = 3
Transitioning data
Don’t Care
1. Each READ command can be issued to any bank. DQM is LOW.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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